Substrate-biased silicon diode for electrostatic discharge protection and fabrication method

ABSTRACT

An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention pertains in general to a semiconductor device,and, more particularly, to a substrate-biased silicon diode and a methodfor making the same.

[0003] 2. Description of the Related Art

[0004] A semiconductor integrated circuit (IC) is generally susceptiblean electrostatic discharge (ESD) event, which may damage or destroy theIC. An ESD event refers to a phenomenon of electrical discharge of acurrent (positive or negative) for a short duration in which a largeamount of current is provided to the IC. The high current may bebuilt-up from a variety of sources, such as the human body. Many schemeshave been implemented to protect an IC from an ESD event. A commonprotection scheme is using a parasitic transistor associated with ann-type metal-oxide semiconductor (MOS) with the source coupled to groundand the drain connected to the pin to be protected from an ESD event.

[0005] Diodes or diode-coupled transistors have been used for ESDprotection in radio-frequency (RF) applications. In a RF IC, an on-chipESD circuit should ideally provide robust ESD protection, whileexhibiting minimum parasitic input capacitance and lowvoltage-dependency. In deep-submicron complementary metal-oxidesemiconductor (CMOS) process technology with shallow-trench isolations(STIs), a diode has been used for ESD protection and is generally formedcontiguous with either an N⁺ or P⁺ diffusion region in a semiconductorsubstrate. FIG. 1A shows a cross-sectional view of a known diode ESDprotection structure formed in an IC. Referring to FIG. 1A, a P⁺diffusion region is bound by STIs on either side, and therefore thediode formed by the STI is also known as an STI-bound diode. TheSTI-bound diode exhibits a bottom capacitance, C_(bottom). However, anSTI-bound diode has been found to have significant leakage current dueto an interference between a silicide layer (not shown) of the P⁺diffusion region and the STIs around the P⁺ region.

[0006]FIG. 1B shows a cross-sectional view of another known diode ESDprotection structure, known as a polysilicon-bound diode, introduced toaddress the leakage current problem with an STI-bound diode. The P⁺diffusion region in a polysilicon-bound diode is now defined by apolysilicon gate, and therefore the leakage current from the edges ofSTIs is eliminated. However, the total parasitic capacitance of thepolysilicon-bound diode is larger than that of the STI-bound diodebecause of the addition of the sidewall junction capacitance of the P⁺diffusion region.

[0007]FIG. 2 is a circuit diagram showing a known ESD protection schemeusing dual diodes. Referring to FIG. 2, the combination of thedual-diode structures and V_(DD)-to-V_(SS) ESD clamp circuit provides apath for an ESD current 2 to discharge, instead of through the internalcircuits. When ESD current 2 is provided to signal a pad PAD1, and witha signal pad PAD2 relatively grounded, ESD current 2 is conducted toV_(DD) through Dp1. ESD current 2 is discharged to V_(SS) through theV_(DD)-to-V_(SS) ESD clamp circuit and flows out of the IC from Dn2 toPAD2. Diode Dp1 has a capacitance of Cp1 and diode Dn1 has a capacitanceof Cn1. The total input capacitance C_(in) of the circuit shown in FIG.2 primarily comes from the parasitic junction capacitance of diodes, andis calculated as follows:

C _(in) =Cp 1 +Cn 1

[0008] wherein Cp1 and Cn1 are parasitic junction capacitances of diodesDp1 and Dn1, respectively.

[0009]FIG. 3 is plot showing the relationship between a pad voltage andparasitic input capacitance of the circuit shown in FIG. 2. Referring toFIG. 3, when the voltage on the pad increases, the parasitic junctioncapacitance of Dp1 increases and the parasitic junction capacitance ofDn1 decreases. Therefore, the total input parasitic capacitance C_(in)is nearly constant. This characteristic is important in RF applications.However, the total parasitic capacitance of a polysilicon-bound diode,as compared to an STI-bound diode, is increased because of the additionof a sidewall capacitance, C_(sidewall), as shown in FIG. 1B.

SUMMARY OF THE INVENTION

[0010] Accordingly, the present invention is directed to asubstrate-biased silicon diode and a method for making the same thatsubstantially obviates one or more of the problems due to limitationsand disadvantages of the related art.

[0011] Additional features and advantages of the invention will be setforth in the description which follows, and in part will be apparentfrom the description, or may be learned by practice of the invention.The objectives and other advantages of the invention will be realizedand attained by the structures and methods particularly pointed out inthe written description and claims thereof, as well as the appendeddrawings.

[0012] To achieve these and other advantages, and in accordance with thepurpose of the invention as embodied and broadly described, there isprovided an integrated circuit device that includes a semiconductorsubstrate, a well region formed inside the semiconductor substrate, afirst isolation structure formed inside the well region, a secondisolation structure formed inside the well region and spaced apart fromthe first isolation structure, a dielectric layer disposed over the wellregion, and a layer of silicon, formed over the dielectric layer,including a p-type portion, an n-type portion and a center portiondisposed between the p-type and n-type portions, wherein the p-typeportion overlaps the first isolation structure and the n-type portionoverlaps the second isolation structure.

[0013] Also in accordance with the present invention, there is providedan integrated circuit device receiving signals from a signal pad thatincludes at least one substrate-biased silicon diode responsive to thesignals from the signal pad for providing electrostatic dischargeprotection from the signals.

[0014] In one aspect of the invention, each of the at least onesubstrate-biased silicon diode includes a p-type silicon portion, ann-type silicon portion and a center silicon portion disposed between andcontiguous with the p-type and n-type silicon portions.

[0015] In another aspect of the invention, there additionally includes adetection circuit for detecting the signals from the signal pad andproviding a bias voltage to the at least one substrate-biased silicondiode.

[0016] Further in accordance with the present invention, there isprovided an integrated circuit device receiving signals from a signalpad that includes a first plurality of serially coupled substrate-biasedsilicon diodes responsive to the signals from the signal pad forproviding electrostatic discharge protection from the signals, each ofthe first plurality of substrate-biased silicon diodes including ap-portion and an n-portion, a second plurality of serially coupledsubstrate-biased silicon diodes responsive to the signals from thesignal pad for providing electrostatic discharge protection from thesignals, each of the second plurality of substrate-biased silicon diodesincluding a p-portion and an n-portion, and a detection circuit fordetecting signals from the signal pad and providing a bias voltage tothe first and second plurality of substrate-biased silicon diodes,wherein the signal pad is coupled to the p-portion of one of the firstplurality of substrate-biased silicon diodes and the n-portion of one ofthe second plurality of the substrate-biased silicon diodes.

[0017] Additionally in accordance with the present invention, there isprovided an integrated circuit device that comprises a semiconductorsubstrate, an insulator layer disposed over the semiconductor substrate,a silicon layer disposed over the insulator layer, which includes afirst isolation structure formed inside the silicon layer, and a secondisolation structure formed inside the silicon layer and spaced apartfrom the first isolation structure, a dielectric layer disposed over thesilicon layer, and a layer of silicon, disposed over the dielectriclayer, which includes a p-type portion, an n-type portion and a centerportion disposed between and contiguous with the p-type and n-typeportions.

[0018] Further in accordance with the present invention, there isprovided a silicon-on-insulator circuit device receiving signals from asignal pad that includes at least one base-biased silicon diode,responsive to the signals from the signal pad, for providingelectrostatic discharge protection.

[0019] In one aspect of the invention, the silicon-on-insulator isbiased to control the at least one base-biased silicon diode.

[0020] Additionally in accordance with the present invention, there isprovided a method for protecting a silicon-on-insulator device fromelectrostatic discharge that includes the steps of providing a signal tothe device through a silicon-on-insulator circuit, providing abase-biased silicon diode in the silicon-on-insulator circuit, andprotecting the device from electrostatic discharge produced with thebase-biased silicon diode.

[0021] Also in accordance with the present invention, there is provideda method for protecting a complementary metal-oxide semiconductor devicefrom electrostatic discharge that includes the steps of providing asignal to the device through a complementary metal-oxide semiconductorcircuit, providing a substrate-biased silicon diode in the complementarymetal-oxide semiconductor circuit, and protecting the device fromelectrostatic discharge produced from the signal with thesubstrate-biased silicon diode.

[0022] Moreover in accordance with the present invention, there isprovided a method for forming a silicon diode that includes the steps ofA method for forming a silicon diode, comprising the steps of forming afirst silicon layer, forming a first isolation structure and a secondisolation structure inside the first silicon layer, the first isolationstructure being spaced apart from the second isolation structure,forming a dielectric layer over the silicon layer, forming a secondsilicon layer over the dielectric layer, forming dielectric spacerscontiguous with the second silicon layer, implanting a first impurityhaving a first concentration into a first portion and a second portionof the second silicon layer, the first portion being contiguous with thesecond portion and the second portion overlapping a region of the firstsilicon layer between the first isolation structure and the secondisolation structure, implanting a first impurity having a secondconcentration into the first portion of the second silicon layer,wherein the second concentration is greater than the firstconcentration, and implanting a second impurity into a third portion ofthe second silicon layer, wherein the third portion is contiguous withthe second portion.

[0023] In one aspect of the invention, the steps of implanting a firstimpurity having a first concentration and implanting a first impurityhaving a second concentration create a diffused region adjacent one offirst and second field isolation structures.

[0024] Also in accordance with the present invention, there is provideda method for forming a base-biased silicon diode that includes the stepsof forming a first and second isolation structures inside a siliconlayer, defining a base region inside the silicon layer, the base regionbeing disposed between and contiguous with the first and secondisolation structures, forming a dielectric layer over the well region,forming a layer of silicon over the dielectric layer, implanting a firstimpurity having a first concentration into a first portion and a secondportion of the silicon layer, wherein the first portion is contiguouswith the second portion and the second portion overlapping a region ofthe silicon layer between the first isolation structure and the secondisolation structure, implanting a first impurity having a secondconcentration into the first portion and second portion of the siliconlayer, wherein the second concentration is greater than the firstconcentration, and implanting a second impurity into a third portion ofthe silicon layer, wherein the third portion is contiguous with thesecond portion and overlaps the second isolation structure.

[0025] Further in accordance with the present invention, there isprovided a method for forming a substrate-biased silicon diode thatincludes the steps of forming a first isolation structure and a secondisolation structure spaced apart from the first isolation structureinside a silicon layer, forming a dielectric layer over the siliconlayer, forming a layer of silicon having two ends over the dielectriclayer, forming dielectric spacers contiguous with the two ends of thesilicon layer, implanting a first impurity having a first concentrationinto a first portion and a second portion of the silicon layer, whereinthe first portion is contiguous with the second portion and overlaps thefirst isolation structure, implanting a second impurity into a thirdportion of the silicon layer, wherein the third portion is contiguouswith the second portion and overlaps the second isolation structure, andimplanting a first impurity having a second concentration into the firstportion of the silicon layer, wherein the second concentration isgreater than the first concentration.

[0026] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory and are intended to provide farther explanation of theinvention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in andconstitute a part of this specification, illustrate embodiments of theinvention and, together with the description, serve to explain theobjects, advantages, and principles of the invention.

[0028] In the drawing:

[0029]FIG. 1A shows a cross-sectional view of a known diode structureformed in an integrated circuit;

[0030]FIG. 1B shows a cross-sectional view of another known diodestructure formed in an integrated circuit;

[0031]FIG. 2 is a circuit diagram of a known ESD protection circuit;

[0032]FIG. 3 is plot showing the relationship between a pad voltage andparasitic input capacitance of the circuit shown in FIG. 2;

[0033]FIG. 4 shows a cross-sectional view of a silicon diode inaccordance with one embodiment of the present invention;

[0034]FIG. 5 shows a cross-sectional view of a silicon diode inaccordance with another embodiment of the present invention;

[0035]FIG. 6 shows a cross-sectional view of a base-biased silicon diodein accordance with one embodiment of the present invention;

[0036]FIG. 7 is a layout diagram of the base-biased silicon diode ofFIG. 5;

[0037] FIGS. 8A-8H are cross-sectional views of the steps in a method offorming a substrate-biased silicon diode with an n-type center region;

[0038] FIGS. 9A-9H are cross-sectional views of the steps in a method offorming a substrate-biased silicon diode with a p-type center region;

[0039]FIG. 10 shows the circuit symbol for the substrate-biased silicondiode of the present invention relative to the cross-sectional view ofthe diode;

[0040]FIG. 11 is a circuit diagram of an ESD protection circuit withdual substrate-biased silicon diodes of the present invention;

[0041]FIG. 12A is plot showing the relationship between a pad voltageand individual parasitic input capacitance of the dual substrate-biasedsilicon diodes of FIG. 10;

[0042]FIG. 12B is plot showing the relationship between a pad voltageand total parasitic input capacitance of the dual substrate-biasedsilicon diodes of FIG. 10;

[0043]FIG. 13A is a circuit diagram of one embodiment of an ESDprotection circuit using substrate-biased silicon diodes of the presentinvention;

[0044]FIG. 13B is a circuit diagram of one embodiment of an ESDprotection circuit using stacked substrate-biased silicon diodes of thepresent invention;

[0045]FIG. 13C is a circuit diagram of another embodiment of an ESDprotection circuit using stacked substrate-biased silicon diodes of thepresent invention; and

[0046]FIG. 14 is a circuit diagram of one embodiment of an ESDprotection circuit with biased dual substrate-biased silicon diodes ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] In accordance with the present invention, there is provided asubstrate-biased polysilicon diode (SBPD) for ESD protection. The SBPDof the present invention is biased from the substrate for an improvedturn-on speed of the SBPD and reduced leakage current. Unlikeconventional diodes, an SBPD does not have a bottom junction capacitanceand therefore exhibits a relatively smaller junction capacitance. Inaddition, because an SBPD is disposed over shallow trench isolations(STIs) in a silicon substrate, the silicon area used by the SBPD isreduced, which reduces cost. The SBPD of the present inventionadditionally provides a substrate-biased function, and thereforeprovides more flexibility in RF IC applications.

[0048]FIG. 4 shows a cross-sectional view of an SBPD in accordance withone embodiment of the present invention. Referring to FIG. 4, anintegrated circuit 10 includes a semiconductor substrate 12 and a wellregion 14 formed inside semiconductor substrate 12. Two isolationstructures 16 are formed inside well region 14 and are spaced apart fromone another. Isolation structures may be conventional STIs used fordevice isolation. Integrated circuit 10 also includes a diffused region20 adjacent one of STIs 16. Diffused region 20 is doped with the sametype of impurity as well region 14. Integrated circuit 10 may alsoinclude another diffused region 18 adjacent one of STIs 16. In oneembodiment of the invention, semiconductor substrate 12 is a p-typesubstrate, well region 14 is an n-well, and diffused region 20 is ann-type diffused region. The optional diffused region 18 is a p-typediffused region.

[0049] A dielectric layer 22 is formed over the well region 14,overlapping STIs 16 and a portion of well region 14A disposed betweenSTIs 16. Dielectric layer 22 may be an oxide layer. A layer of silicon32, subsequently becomes an SBPD, is disposed over dielectric layer 22.Silicon layer 32 includes a p-type portion 24, an n-type portion 26, anda center portion 28 disposed between p-type portion 24 and n-typeportion 26. P-type portion 24 overlaps one of STIs 16 and n-type portion26 overlaps the other one of STIs 16. Center portion 28 overlaps wellregion portion 14A. In one embodiment, center portion 28 of siliconlayer 32 is doped with an n-type impurity having a doped concentrationlower than that of n-type portion 26. In another embodiment, centerportion 28 of silicon layer 32 is doped with a p-type impurity having adoped concentration lower than that of p-type portion 24. In addition,in an embodiment in which diffused region 20 is an n-type diffusedregion, diffused region 20 is adjacent one of STIs 16 and n-type portion26 of silicon layer 32. A plurality of contacts 30 are formed insidediffused region 20, p-type portion 24 and n-type portion 26 of siliconlayer 32.

[0050] In operation, SBPD 32 responds to ESD pulses to provideelectrostatic discharge protection. Furthermore, well region 14 can bebiased to control SBPD 32. In one embodiment, diffused region 20 isbiased to cause well region 14 to be biased to control SBPD 32 forproviding electrostatic discharge protection.

[0051]FIG. 5 shows a cross-sectional view of a silicon diode inaccordance with another embodiment of the present invention. Referringto FIG. 5, an integrated circuit 200 includes a semiconductor substrate202 and a dielectric layer 204 formed over semiconductor substrate 202.Dielectric layer 204 may comprise a conventional STI. Integrated circuit200 also includes a layer of silicon 206, subsequently becomes a silicondiode, is disposed over dielectric layer 204. Silicon layer 206 includesa p-type portion 208, an n-type portion 210, and a center portion 212disposed between p-type portion 208 and n-type portion 210. In oneembodiment, center portion 212 is undoped and may be fabricated in asalicide CMOS process. The silicon diode thus formed has no junction insemiconductor substrate 202, eliminating substrate noise coupling.

[0052]FIG. 6 shows a cross-sectional view of a base-biased silicon diodein accordance with another embodiment of the present invention.Referring to FIG. 6, the SBPD of the present invention is implemented ina silicon-on-insulator (SOI) CMOS integrated circuit 34. An insulator 38is disposed over a semiconductor substrate 36. A silicon layer 40 isdisposed over insulator layer 38 and includes an isolation structure 42formed inside silicon layer 40 and an isolation structure 44 formedinside silicon layer 40 and spaced apart from isolation structure 42.Silicon layer 40 also includes a base portion 46 disposed between andcontiguous with isolation structures 42 and 44. In one embodiment of thepresent invention, substrate 36 is a p-type substrate, and isolationstructures 42 and 44 are STIs.

[0053] A dielectric layer (not shown) is disposed over silicon layer 40,and a layer of polysilicon 52 is disposed over the dielectric layer.Polysilicon layer 52 may also be a silicon layer. Polysilicon layer 52includes a p-type portion 50, an n-type portion 48 and a center portion(not shown) disposed between and contiguous with the p-type and n-typeportions 48 and 50. In addition, p-type portion 50 overlaps isolationstructure 44 and n-type portion 48 overlaps isolation structure 42. Thecenter portion of polysilicon layer 52 overlaps base portion 46.Integrated circuit 34 may additional comprise a diffused region (notshown) inside silicon layer 40 adjacent one of isolation structures 42and 44. Integrated circuit 34 also comprises a plurality of contacts 54.

[0054] In operation, insulator layer 38 isolates devices in SOIintegrated circuit 34. Thus, silicon diode 52 of the present inventionis adapted to be base-biased. The bias supply for based-biased silicondiode 52 may be located on one or both sides of based-biased silicondiode 52 in the form of diffused region adjacent one of isolationstructure 42 and 44. Base portion 46 of silicon layer 40 may also bebiased to control based-biased silicon diode 52 to provide electrostaticdischarge protection. Therefore, this embodiment of the presentinvention appropriately named a base-biased silicon diode. FIG. 7 is alayout diagram of base-biased silicon diode 52 as shown in FIG. 6 alongthe A-A′ direction.

[0055] FIGS. 8A-8H are cross-sectional views of the steps in a method offorming a substrate-biased silicon diode of the present invention.Referring to FIG. 8A, a semiconductor substrate 12 is prepared anddefined. In one embodiment, semiconductor substrate 12 is a p-typesubstrate. FIG. 8B shows the formation of STIs 16 inside semiconductorsubstrate 12. In general, STIs are formed by providing a mask over asubstrate. After the mask is patterned and defined, the semiconductorsubstrate is etched to form shallow trenches spaced apart from oneanother. A dielectric material, such as silicon dioxide, silicon-nitrideor silicon oxynitride, is deposited to fill the trenches. The mask isthen removed.

[0056]FIG. 8C shows an implantation of impurities to form a well region.Referring to FIG. 8C, after a photoresist 56 is patterned and defined,substrate 12 is doped with an impurity to form well 14. In oneembodiment, substrate 12 is doped with an n-type impurity to form ann-well. After implantation, photoresist 56 is removed.

[0057]FIG. 8D shows the beginning of the formation of a silicon diode.Referring to FIG. 8D, a thin oxide layer 58 is grown over the surface ofwell region 14. A layer of silicon 32 is then deposited over oxide layer58. A photoresist (not shown) is used to pattern and define siliconlayer 32 during an etching process to form the structure shown in FIG.8D. Conventional steps follow to form spacers 62 contiguous with siliconlayer 32. Spacers 62 may be oxide spacers or nitride spacers.

[0058] Referring to FIG. 8E, a photoresist 64 is deposited over siliconlayer 32, spacers 62, well 14, and substrate 12, and then patterned anddefined to expose a first portion 26 of silicon layer 32, a portion ofsilicon layer 32 that would later become center portion 28, and aportion of well 14. A lightly-doped drain ADD) of an impurity isimplanted into first portion 26, center portion 28, and the exposedportion of well 14. The implanted impurity forms a diffused region 20 inwell region 14. Therefore, first portion 26 contains the same type ofimpurity as center portion 28 and diffused region 20. In one embodiment,an LDD of an n-type impurity is implanted into first portion 26, centerportion 28, and diffused portion 20.

[0059] Referring to FIG. 8F, a photoresist 65 is deposited over siliconlayer 32, spacers 62, well 14, and substrate 12, and then patterned anddefined to expose first portion 26 and diffused region 20. A highconcentration of the same type of impurity implanted in FIG. 8E isimplanted into first portion 26 and diffused region 20. The highconcentration implant of FIG. 8F provides a higher concentration thanthe LDD implant of FIG. 8E. Diffused region 20 is implanted with thesame type of impurity as first portion 26. After the high concentrationimplantation, diffused region 20 diffuses further into well 14,and-first portion 26 now contains a higher concentration of impurity.Therefore, center portion 28 contains a lower concentration ofimpurities than first portion 26. Photoresist 65 is then removed. In oneembodiment, a high concentration of an n-type impurity is implanted, andfirst portion 26 becomes the n-portion of an SBPD.

[0060] Referring to FIG. 8G, a photoresist 66 is deposited over siliconlayer 32, spacers 62, well 14, and substrate 12. Photoresist 66 ispatterned and defined to expose a second portion 24 of silicon layer 32.An impurity of a different type than the LDD and high concentrationimplants of FIGS. 8E and 8F is implanted into second portion 24. Secondportion 24 is heavily doped with the different impurity. In oneembodiment, second portion 24 is heavily doped with a p-type impurityand become the p-portion of an SBPD. Photoresist 66 is then removed.Referring to FIG. 8H, conventional semiconductor processing follows toform a plurality of contacts 30.

[0061] Similar to the method of forming an SBPD shown in FIGS. 8A-8Habove, FIGS. 9A-9H are cross-sectional views of the steps in a method offorming a substrate-biased silicon diode with a p-type center region.Referring to FIG. 9A, a p-type semiconductor substrate 112 is preparedand defined. FIG. 9B shows the formation of STIs 116 insidesemiconductor substrate 112. STIs 116 may be formed using the processsteps described above. FIG. 9C shows an n-well implantation to t form ann-well region. Referring to FIG. 9C, after a photoresisit 156 ispatterned and defined, substrate 112 is doped with an n-type impurity toform n-well 114. In addition, STIs 116 are now disposed inside n-well114. After implantation, photoresist 156 is removed.

[0062] Referring to FIG. 9D, a thin oxide layer 158 is grown over thesurface of n-well 114. A layer of silicon 132 is then deposited overoxide layer 158. A photoresist (not shown) is used to pattern and definepolysilicon layer 132 during etching to form the structure shown in FIG.9D. Conventional steps follow to form spacers 162 contiguous withpolysilicon layer 132. Spacers 162 may be oxide spacers or nitridespacers.

[0063] Referring to FIG. 9E, after a photoresist 168 is deposited overpolysilicon layer 132, spacers 162, n-well 114, and substrate 112,photoresist 168 is patterned and defined to expose a second portion 124of polysilicon layer 132. A p-type lightly-doped drain (LDD) isimplanted into second portion 124. Photoresist 168 is removed after theimplantation step.

[0064] Referring to FIG. 9F, a photoresist 170 is deposited overpolysilicon layer 132, spacers 162, n-well 114, and substrate 112.Photoresist 170 is patterned and defined to expose a first portion ofpolysilicon layer 126, a portion of polysilicon layer 132 that wouldlater become a center portion 128, and a portion of n-well 1I14. Ahigh-concentration n-type impurity is implanted into first portion 126,center portion 128, and the portion of n-well 114. Implanted portion ofn-well 114 becomes an n-type diffused region 120. Photoresist 170 isthen removed.

[0065] Referring to FIG. 9G, a photoresist 172 is laid down andpatterned. Using photoresist 172 as a mask, a high concentration of ap-type impurity is implanted into second portion 124. The implantationconcentration of the step shown in FIG. 9G is larger than that of theLDD implantation step shown in FIG. 9E. The p-portion 124 of an SBPD isformed and contains a higher impurity concentration than center region128 of the SBPD. Photoresist 172 is then removed. Referring to FIG. 9H,conventional semiconductor processing follows to form a plurality ofcontacts 130.

[0066] For a silicon diode of the present invention manufactured usingan SOI technology, a modification of the manufacturing processesdescribed above will be required. However, the modification will belimited to the few steps at the beginning of the manufacturing processunrelated to the manufacturing steps for the formation of the silicondiode. With the exception of the steps related to the creating of a wellregion, the manufacturing steps described above follow to manufacture abase-biased silicon diode of the present invention as described above.

[0067]FIG. 10 is a circuit symbol for an SBPD of the present inventionrelative to the cross-sectional view of the diode. FIG. 11 is a circuitdiagram of an ESD protection circuit with two dual-SBPDs. The first dualSBPDs include SBPD1 and SBPD2, and second dual SBPDs include SBPD3 andSBPD4. Referring to FIG. 11, dual silicon diodes SBPD1 and SBPD2 areused in a forward-biased condition to discharge an ESD current so thatthe ESD current does not damage the internal circuits. When an ESDcurrent 4 is applied to Pad1, and with Pad2 grounded relative to Pad1,an ESD current 4 is conducted to V_(DD) through silicon diode SBPD1. ESDcurrent 4 is then discharged to the VSS line through a VDD-to-VSS ESDclamp circuit 6 and flows out of the IC through SBPD4.

[0068] Therefore, the present invention also includes a method forprotecting a CMOS semiconductor device from electrostatic discharge. Themethod provides a signal to the semiconductor device through a CMOSsemiconductor circuit that includes at least one substrate-biasedsilicon diode to protect the semiconductor device from electrostaticdischarge. Similarly, the present invention also includes a method forprotecting a silicon-on-insulator semiconductor device fromelectrostatic discharge. The method provides a signal to the devicethrough a silicon-on-insulator circuit that includes at least onebase-biased silicon diode to protect the semiconductor device fromelectrostatic discharge.

[0069]FIG. 12A is plot showing the relationship between a pad voltageand individual parasitic input capacitance of the dual substrate-biasedsilicon diodes of FIG. 11. When the n-well region of an SBPD is biasedto ground, the parasitic capacitance of the SBPD is approximately halfof the polysilicon-bound diode of FIG. 1B because, unlike apolysilicon-bound diode, an SBPD does not have a bottom junctioncapacitance, C_(bottom). As shown in FIG. 12A, the capacitance variationof an SBPD relative to pad voltages is similar to that of apolysilicon-bound diode as shown in FIG. 3. Therefore, the total inputcapacitance C_(in) of the dual SBPDs of FIG. 11 is also approximatelyhalf of the dual polysilicon-bound diodes. This relationship is shown inFIG. 12B.

[0070] The input parasitic capacitance of SBPDs may be further reducedby connecting a plurality of SBPDs in series because capacitancesconnected in series lower the total capacitance. FIG. 13A is a circuitdiagram of one embodiment of an ESD protection circuit using dual SBPDs.Assuming each of the SBPDs has the same capacitance C, the totalcapacitance for FIG. 13A is 2C. FIG. 13B is a circuit diagram of oneembodiment of an ESD protection circuit using two dual-SBPDs. The totalcapacitance for FIG. 13B is C. FIG. 13C is a circuit diagram of anotherembodiment of an ESD protection circuit using dual SBPD strings. Thetotal capacitance for FIG. 13C is 2C/n, wherein n represents the numberof SBPDs.

[0071]FIG. 14 is a circuit diagram of one embodiment of an ESDprotection circuit with biased dual SBPDs of the present invention.Referring to FIG. 14, an integrated circuit device 74 receives signalsfrom a signal pad 76. Device 74 includes a pair of SBPDs 78 and 80,responsive to the signals from signal pad 76 for providing electrostaticdischarge protection from the signals. Each of SBPDs 78 and 80 includesa p-portion and an n-portion (not numbered) and signal pad 76 is coupledto the p-portion of one of the pair of SBPDs and the n-portion of theother one of the pair of SBPDs. In one embodiment of the invention asshown in FIG. 11, device 74 additionally comprises a second pair ofSBPDs, SBPD3 and SBPD4, coupled to clamp circuit 6. In anotherembodiment as shown in FIG. 13C, each of the pair of SBPDs 78 and 80 ofFIG. 14 includes a plurality of serially coupled SBPDs.

[0072] Referring again to FIG. 14, device 74 further comprises adetection circuit 86 for detecting signals from signal pad 76 andproviding a bias voltage to SBPDs 78 and 80. In one embodiment, anintegrated circuit that receives electrostatic charges from a signal padcomprises a plurality of serially coupled SBPDs responsive to theelectrostatic pulses from the signal pad for providing electrostaticdischarge protection from the signals. Detection circuit 78 comprises aresistor-capacitor (R-C) circuit having a delay constant longer than theduration of the electrostatic pulses. The resistor-capacitor circuit iscoupled in parallel with a transistor network. The transistor networkcomprises a first transistor 84, and a second transistor 82, and each ofthe transistors includes a gate, source and drain. The gate of firsttransistor 84 is coupled to the gate of second transistor 82 and theresistor-capacitor circuit. In addition, the drain of first transistor84 and the drain of the second transistor 82 are coupled to a substrateof SBPDs 78 and 80. The source of first transistor 84 is coupled to aVDD signal and the source of second transistor 82 is coupled to a VSSsignal. In operation, the drain of first transistor 84 and the drain ofthe second transistor 82 are coupled to the substrate of SBPDs 78 and 80to provide a bias voltage.

[0073] It will be apparent to those skilled in the art that variousmodifications and variations can be made in the disclosed processwithout departing from the scope or spirit of the invention. Otherembodiments of the invention will be apparent to those skilled in theart from consideration of the specification and practice of theinvention disclosed herein. It is intended that the specification andexamples be considered as exemplary only, with a true scope and spiritof the invention being indicated by the following claims.

What is claimed is:
 1. An integrated circuit device, comprising asemiconductor substrate; a well region formed inside the semiconductorsubstrate; a first isolation structure formed inside the well region; asecond isolation structure formed inside the well region and spacedapart from the first isolation structure; a dielectric layer disposedover the well region; and a layer of silicon, formed over the dielectriclayer, including a p-type portion, an n-type portion and a centerportion disposed between the p-type and n-type portions, wherein thep-type portion overlaps the first isolation structure and the n-typeportion overlaps the second isolation structure.
 2. The integratedcircuit device as claimed in claim 1, wherein the center portion of thelayer of silicon is doped with an n-type impurity having a dopedconcentration lower than that of the n-type portion.
 3. The integratedcircuit device as claimed in claim 1, wherein the center portion of thelayer of silicon is doped with a p-type impurity having a dopedconcentration lower than that of the p-type portion.
 4. The integratedcircuit device as claimed in claim 1, wherein the center portion of thelayer of silicon is undoped.
 5. The integrated circuit device as claimedin claim 1, wherein the center portion overlaps a portion of the wellregion between the first and second isolation structures.
 6. Theintegrated circuit device as claimed in claim 1, further comprising adiffused region formed inside the well region adjacent one of the firstand second isolation structures.
 7. The integrated circuit device asclaimed in claim 6, wherein the diffused region is biased to cause thewell region to be biased to control the silicon layer for providingelectrostatic discharge protection.
 8. An integrated circuit devicereceiving signals from a signal pad, comprising at least onesubstrate-biased silicon diode responsive to the signals from the signalpad for providing electrostatic discharge protection.
 9. The integratedcircuit device claimed in claim 8, wherein the at least onesubstrate-biased silicon diode includes one or more serially coupledsubstrate-biased silicon diodes.
 10. The integrated circuit device asclaimed in claim 8, wherein the at least one substrate-biased silicondiode includes a p-type polysilicon portion, an n-type polysiliconportion and a center polysilicon portion disposed between and contiguouswith the p-type and n-type polysilicon portions.
 11. The integratedcircuit device as claimed in claim 10 further comprising, a firstisolation structure, and a second isolation structure spaced apart fromthe first isolation structure, wherein the p-type polysilicon portionoverlaps the first isolation structure and the n-type polysiliconportion overlaps the second isolation structure.
 12. The integratedcircuit device as claimed in claim 11, further comprising, a diffusedregion inside a well region adjacent one of the first isolationstructure and second isolation structure, wherein the diffused region isdoped with a same impurity as the well region.
 13. The integratedcircuit device as claimed in claim 12, wherein the well region is biasedto control the at least one substrate-biased silicon diode for providingelectrostatic discharge protection.
 14. The integrated circuit device asclaimed in claim 12, wherein the diffused region is biased to cause thewell region to be biased to control the at least one substrate-biasedsilicon diode for providing electrostatic discharge protection.
 15. Theintegrated circuit device as claimed in claim 8, wherein the at leastone substrate-biased silicon diode includes a p-portion and ann-portion, and wherein the signal pad is coupled to the p-portion of theat least one substrate-biased silicon diode.
 16. The integrated circuitdevice as claimed in claim 8, further comprising a detection circuit fordetecting the signals from the signal pad and providing a bias voltageto the at least one substrate-biased silicon diode.
 17. The integratedcircuit device as claimed in claim 8, wherein the signals from thesignal pad are electrostatic pulses.
 18. The integrated circuit deviceas claimed in claim 16, wherein the detection circuit comprises aresistor-capacitor circuit having a delay constant longer than theduration of the signals from the signal pad.
 19. The integrated circuitdevice as claimed in claim 16, wherein the detection circuit comprises aresistor-capacitor circuit coupled in parallel to a transistor network.20. The integrated circuit device as claimed in claim 16, wherein thedetection circuit includes a first transistor, a second transistor, anda resistor-capacitor circuit, and wherein a gate of the first transistoris coupled to a gate of the second transistor and the resistor-capacitorcircuit.
 21. The integrated circuit device as claimed in claim 20,wherein a drain of the first transistor and a drain of the secondtransistor are coupled to a substrate of the at least onesubstrate-biased silicon diode to provide a bias voltage.
 22. Theintegrated circuit device as claimed in claim 20, wherein a source ofthe first transistor is coupled to a V_(DD) signal and a source of thesecond transistor is coupled to a V_(SS) signal.
 23. An integratedcircuit device receiving signals from a signal pad, comprising: a firstplurality of serially coupled substrate-biased silicon diodes responsiveto the signals from the signal pad for providing electrostatic dischargeprotection from the signals, each of the first plurality ofsubstrate-biased silicon diodes including a p-portion and an n-portion;a second plurality of serially coupled substrate-biased silicon diodesresponsive to the signals from the signal pad for providingelectrostatic discharge protection from the signals, each of the secondplurality of substrate-biased silicon diodes including a p-portion andan n-portion; and a detection circuit for detecting signals from thesignal pad and providing a bias voltage to the first and secondplurality of substrate-biased silicon diodes, wherein the signal pad iscoupled to the p-portion of one of the first plurality ofsubstrate-biased silicon diodes and the n-portion of one of the secondplurality of the substrate-biased silicon diodes.
 24. The integratedcircuit device as claimed in claim 23, wherein the detection circuitcomprises a first transistor; a second transistor, and aresistor-capacitor network, and wherein a gate of the first transistoris coupled to a gate of the second transistor and the resistor-capacitorcircuit.
 25. The integrated circuit device as claimed in claim 24,wherein a drain of the first transistor and a drain of the secondtransistor-are coupled to a substrate of the first and second pluralityof substrate-biased silicon diodes to provide a bias voltage to thefirst and second plurality of substrate-biased silicon diodes.
 26. Anintegrated circuit device, comprising a semiconductor substrate; aninsulator layer disposed over the semiconductor substrate; a siliconlayer disposed over the insulator layer, including a first isolationstructure formed inside the silicon layer, and a second isolationstructure formed inside the silicon layer and spaced apart from thefirst isolation structure; a dielectric layer disposed over the siliconlayer; and a layer of silicon, disposed over the dielectric layer,including a p-type portion, an n-type portion and a center portiondisposed between and contiguous with the p-type and n-type portions. 27.The integrated circuit device as claimed in claim 26, wherein the centerportion of the layer of silicon overlaps a portion of the silicon layerbetween the first and second isolation structures.
 28. The integratedcircuit device as claimed in claim 26, wherein the portion of thesilicon layer between the first and second isolation structures isbiased to provide electrostatic discharge protection.
 29. Asilicon-on-insulator circuit device receiving signals from a signal pad,comprising at least one base-biased silicon diode, responsive to thesignals from the signal pad, for providing electrostatic dischargeprotection.
 30. The silicon-on-insulator circuit device as claimed inclaim 29, wherein each of the at least one base-biased silicon diodesincludes a p-type polysilicon portion, an n-type polysilicon portion anda center polysilicon portion disposed between and contiguous with thep-type and n-type polysilicon portions.
 31. The silicon-on-insulatorcircuit device as claimed in claim 29, wherein the silicon-on-insulatorcircuit device is biased to control the at least one base-biased silicondiode.
 32. An integrated circuit device receiving signals from a signalpad, comprising one or more serially coupled base-biased silicon diodes,responsive to the signals from the signal pad, for providingelectrostatic discharge protection.
 33. The integrated circuit device asclaimed in claim 32, further comprising a detection circuit fordetecting signals from the signal pad and providing a bias voltage tothe one or more base-biased silicon diodes, wherein the detectioncircuit comprises a resistor-capacitor network coupled in parallel to atransistor network.
 34. The integrated circuit device as claimed inclaim 33, wherein the transistor network includes a first transistor anda second transistor, and wherein a gate of the first transistor iscoupled to a gate of the second transistor and the resistor-capacitornetwork, and wherein a drain of the first transistor and a drain of thesecond transistor are coupled to a base of the one or more base-biasedsilicon diodes to provide a bias voltage.
 35. A method for protecting asilicon-on-insulator device from electrostatic discharge, comprising thesteps of: providing a signal to the device through asilicon-on-insulator circuit; providing a base-biased silicon diode inthe silicon-on-insulator circuit; and protecting the device fromelectrostatic discharge with the base-biased silicon diode.
 36. A methodfor protecting a complementary metal-oxide semiconductor device fromelectrostatic discharge, comprising the steps of: providing a signal tothe device through a complementary metal-oxide semiconductor circuit;providing a substrate-biased silicon diode in the complementarymetal-oxide semiconductor circuit; and protecting the device fromelectrostatic discharge produced from the signal with thesubstrate-biased silicon diode.
 37. A method for forming a silicondiode, comprising the steps of: forming a first silicon layer; forming afirst isolation structure and a second isolation structure inside thefirst silicon layer, the first isolation structure being spaced apartfrom the second isolation structure; forming a dielectric layer over thesilicon layer; forming a second silicon layer over the dielectric layer;forming dielectric spacers contiguous with the second silicon layer;implanting a first impurity having a first concentration into a firstportion and a second portion of the second silicon layer, the firstportion being contiguous with the second portion and the second portionoverlapping a region of the first silicon layer between the firstisolation structure and the second isolation structure; implanting afirst impurity having a second concentration into the first portion ofthe second silicon layer, wherein the second concentration is greaterthan the first concentration; and implanting a second impurity into athird portion of the second silicon layer, wherein the third portion iscontiguous with the second portion.
 38. The method as claimed in claim37, wherein the silicon layer is a semiconductor substrate.
 39. Themethod as claimed in claim 37, further comprising a step of forming awell region inside the semiconductor substrate, wherein the first andsecond isolation structures are disposed inside the well region.
 40. Themethod as claimed in claim 37, wherein the first impurity is an n-typeimpurity and the second impurity is a p-type impurity.
 41. The method asclaimed in claim 37, wherein the first impurity is a p-type impurity andthe second impurity is an n-type impurity.
 42. The method as claimed inclaim 37, wherein the step of forming a first and second isolationstructures comprises the steps of forming a first trench and a secondtrench spaced apart from the first trench in the silicon layer, andproviding a dielectric material in the first and second trenches. 43.The method as claimed in claim 37, wherein the step of forming adielectric layer includes a step of growing an oxide layer.
 44. Themethod as claimed in claim 37, wherein the steps of implanting a firstimpurity having a first concentration and implanting a first impurityhaving a second concentration create a diffused region adjacent one offirst and second field isolation structures.
 45. The method as claimedin claim 37, wherein the step of implanting a first impurity having afirst concentration includes the steps of providing a photoresist overthe first silicon layer and the second silicon layer, patterning anddefining the photoresist to expose the first portion and the secondportion of the second silicon layer, implanting the first impurity intothe first portion and the second portion, and removing the photoresist.46. The method as claimed in claim 37, wherein the step of implanting asecond impurity includes the steps of providing a photoresist over thesecond silicon layer and the silicon layer, patterning and defining thephotoresist to expose the third portion of the second silicon layer,implanting the second impurity into the third portion, and removing thephotoresist.
 47. The method as claimed in claim 37, farther comprising:defining a substrate; forming a layer of insulator over the substrate;and forming the layer of silicon over the insulator layer.
 48. A methodfor forming a base-biased silicon diode, comprising the steps of:forming a first and second isolation structures inside a silicon layer;defining a base region inside the silicon layer, the base region beingdisposed between and contiguous with the first and second isolationstructures; forming a dielectric layer over the well region; forming alayer of silicon over the dielectric layer; implanting a first impurityhaving a first concentration into a first portion and a second portionof the silicon layer, wherein the first portion is contiguous with thesecond portion and the second portion overlapping a region of thesilicon layer between the first isolation structure and the secondisolation structure; implanting a first impurity having a secondconcentration into the first portion and second portion of the siliconlayer, wherein the second concentration is greater than the firstconcentration; and implanting a second impurity into a third portion ofthe silicon layer, wherein the third portion is contiguous with thesecond portion and overlaps the second isolation structure.
 49. Themethod as claimed in claim 48, wherein the silicon layer is a siliconlayer of a silicon-on-insulator structure.
 50. A method for forming asubstrate-biased silicon diode, comprising the steps of: forming a firstisolation structure and a second isolation structure spaced apart fromthe first isolation structure inside a silicon layer; forming adielectric layer over the silicon layer; forming a layer of siliconhaving two ends over the dielectric layer; forming dielectric spacerscontiguous with the two ends of the silicon layer; implanting a firstimpurity having a first concentration into a first portion and a secondportion of the silicon layer, wherein the first portion is contiguouswith the second portion and overlaps the first isolation structure;implanting a second impurity into a third portion of the silicon layer,wherein the third portion is contiguous with the second portion andoverlaps the second isolation structure; and implanting a first impurityhaving a second concentration into the first portion of the siliconlayer, wherein the second concentration is greater than the firstconcentration.
 51. The method as claimed in claim 50, wherein the stepof implanting a second impurity creates a diffused region adjacent oneof first and second field isolation structures.
 52. An integratedcircuit device used for electrostatic discharge protection, comprising:a semiconductor substrate; a dielectric layer disposed over thesubstrate; and a layer of silicon, formed over the dielectric layer,including a p-type portion and an n-type portion.
 53. An integratedcircuit device used for electrostatic discharge protection, comprising:a semiconductor substrate; a dielectric layer disposed over thesubstrate; a layer of silicon, formed over the dielectric layer,including a p-type portion, an n-type portion, and a center portiondisposed between the n-type and p-type portions.